1. Field of the Invention
This invention relates to semiconductor devices and more particularly to EEPROM devices.
2. Description of Related Art
EEPROM (Electrically Erasable Programmable Read Only Memory) devices are well known in the art, as described in U.S. Pat. No. 5,077,691 of Haddad et al for "Flash EEPROM array with Negative Gate Voltage Erase Operation."
U.S. Pat. No. 5,029,130 of Yeh for "Single Transistor Non-Volatile Electrically Alterable Semiconductor Memory Device" stating that "local enhancement of the electric field can be due to the unsmoothed grain size of the floating gate 22 or asperity on the floating gate 22 which is typically made of polysilicon . . . ." The insulating dielectric beneath the floating gate is formed by thermally growing silicon oxide, silicon nitride, or silicon oxynitride from 50 .ANG. to 200 .ANG. thick. Then a LPCVD layer of amorphous silicon is deposited upon the insulation dielectric. Next a silicon nitride dielectric layer is deposited, followed by treatment in a diffusion furnace, converting the amorphous silicon into single crystalline silicon. A patent related to the Yeh patent is U.S. Pat. No. 5,067,108 of Jenq for "Single Transistor Non-Volatile Electrically Alterable Semiconductor Memory Device with a Re-crystallized Floating Gate."
Because of the tunneling oxide window, the cell size of the conventional EEPROM cell is very large. The programmability of a triple polysilicon cell is not consistent.
A conventional FLOTOX (FLOating Gate Tunnel OXide) cell is large in size but easy to produce. The Flotox device includes a tunneling window opened by lithography to form the floating gate in proper alignment with an N+ ion implanted region in the substrate, which is also formed by use of photolithographic steps. Accordingly, since production of such a Flotox device requires several photolithographic steps, there are alignment problems.